Signal recognition system



Sept. 1 1964 Filed June 15, 1961 B. W. MEYER ETAL SIGNAL RECOGNITIONSYSTEM FIG. [2

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Sept. 1, 1964 B. w. MEYER ETAL 3,147,343

SIGNAL RECOGNITION SYSTEM Filed June 15, 1961 15 Sheets-Sheet 15 SE C70/? ADDRESS C50 (5/ D7) (57+ 07) ($2 5:?) (BY-+08) (53 0 9) (5+ 09)(3407) (8 1+ 0/0) United States Patent 3,147,343 SIGNAL REQUGNKTHQNSYSTEF/l Burtis W. Meyer, halo Alto, and George M. Miller, MountainView, (Iaiifi, assignors to General Electric Company, a corporation ofNew York Filed June 15, 1961, Ser. No. 117,324 13 Claims. (Cl. l'791)This invention relates to signal recognition systems and particularly tosuch systems for recognizing signals which have been developed fromspoken language.

Many machines which are now controlled by some form of key board inputcould be operated faster and more efiiciently if the operator couldmerely speak the information into a microphone. Spoken language iscomposed of basic sounds, each having a characteristic frequencycomponent, which are called phonemes. Examples of phonemes are thesounds of the letters m, n and r. Some combinations of letters in theEnglish language are spoken as a single phoneme such as the th in think.Other letters, mainly the vowels, may be spoken as several differentphonemes depending on the word in which they appear. For example, the oin two is a different phoneme than the o in top. A spoken word isrecognized by the sequence of phonemes which it contains.

Devices are known in the art for detecting the phonemes of spokenlanguage. In such devices electrical signals from a microphone areapplied to a bank of frequency selective filters. The filtercorresponding to the predominant frequency component of the spokenphoneme will have the highest output signal. This highest signal maythen be detected to produce a corresponding phoneme signal on one of aplurality of phoneme output lines. Such a device is shown, for example,in a US. Patent No. 2,646,465, issued to K. H. Davis et al., July 21,1953, for a Voice-Operated System.

The above-mentioned devices thus detect the phonemes of a word as theyare spoken and produce a corresponding sequence of phoneme signals.Signal recognition apparatus is then required to store the sequence ofphonemes of a word and to compare the phonemes of the sequence to storedstandard phoneme sequences. Once an identity between the receivedphoneme sequence and the stored standard phoneme sequence is found acorresponding word designator signal can then be produced to carry outthe operations desired.

While the basic principles of the system are straightforward severalproblems are encountered. For example: short periods of silence withinthe enunciation of a word can be significant and for this reason silenceis one of the phonemes to be recognized. Examples of significantsilences are those which always proceed an explosive phoneme, such as p,b, and t. However, the system must provide some means for recognizingsignificant silence and distinguishing it from mere absence of input.Another problem is the Wide variation in speaking speed with the resultthat a phoneme may persist over a variable length of time. Thus if aphoneme is spoken slowly there must be provision for preventing it frombeing construed as more than one phoneme. On the other hand, shortduration noise and transient signals should not be erroneouslyidentified as phonemes. A further problem arises from the well-knownfact that a given word may be spoken in several ways, thus giving riseto several different phoneme sequences all having the .same meaning. Itis, of course, desirable that the phoneme signal recognition systemshall produce the same machine output signal for each of these diiferentphoneme sequences. It is also desirable to provide a system in which thestored ice phoneme sequences can be readily altered or changed tocorrespond to the speech of the operator.

It is therefore an object of the invention to provide an improvedphoneme signal recognition system.

It is a further object of the invention to recognize as phoneme signalsonly signals which have persisted for a predetermined minimum period.

Another object of the invention is to recognize a lengthy phoneme signalas only one phoneme.

Another object of the invention is to correctly recognize a word whichmay be spoken in one of several alternative ways.

Another object of the invention is to provide ready change of the storedphoneme sequences,

Another object of the invention is to store a representation of thephoneme sequence of a word as spoken by an operator.

These and other objects of the invention are achieved in a system whichreceives the successive phoneme signals as they are developed by aphoneme detector in response to a spoken word. The phoneme signals areexamined periodically at successive sample times and the phoneme presentat a given sample time is accepted if it has persisted for apredetermined number of sample times (thus eliminating short periodnoise and transient signals) and if it is different from the phonemelast accepted (thereby accounting for slowly spoken phonemes).

The accepted phonemes are assembled in a temporary storage device andwhen the spoken word has ended this assembled sequence of phonemes iscompared with a set of phoneme sequences stored in a memory whichconstitutes a dictionary of all of the allowable ways of speaking eachword of the vocabulary of words to be recognized.

Associated with each of the phoneme sequencies stored in the memory is aWord designator which is a machine language representation of thecorresponding spoken word. When a comparison is found between theassembled sequence of phonemes and a stored phoneme sequence in thememory, the associated word designator is made available as amanifestation of the identity of the corresponding spoken word and itmay then be used for control of external equipment or the like.

Provision is also made for changing the stored phoneme sequences in thememory so that representations of new Words or different ways ofpronouncing the same word may be stored therein. To do this the desiredword is spoken into the microphone of the phoneme detector and thesystem assembles the sequence of phonemes as described above. Thissequence of phonemes is then transferred to a pre-selected address inthe memory unit along with a corresponding Word designator.

The invention will be more specifically described with reference to thefollowing drawings in which:

FIGURE 1 is a block diagram of the phoneme signal recognition system ofthe invention;

FIGURE 2 is a symbolic illustration'of an AND gate together with itscorresponding logic equation;

FIGURE 3 is a symbolic illustration of an OR gate together with itscorresponding logic equation;

FIGURE 4 is a block diagram of a flip-flop circuit;

FIGURE 5 is a symbolic illustration of the flip-flop circuit of FIG. 4;

FIGURE 6 is a symbolic illustration of a clock pulse driver circuit;

FIGURE 7 is a symbolic illustration of an amplifierinverter forproducing complementary output signals;

FIGURE 8 is a symbolic illustration of a monostable or one-shot circuit;

FIGURE 9 is a chart showing the binary encoding of the phoneme signalsfrom the phoneme detector;

FIGURE is an illustration of an encoder structure in logic equationform;

FIGURE 11 is an illustration of a register circuit (A- register) withthe input logic circuit thereof shown in logic equation form;

FIGURE 12 is an illustration of a register circuit (B- register) withthe input logic circuit thereof shown in logic equation form;

FIGURE 13 is a block diagram together with the logic equation of a logiccircuit for comparing the phoneme representations in the A and Bregisters;

FIGURE 14 is a block diagram together with the logic equation of a logiccircuit for comparing the phoneme representation in A-register with thephoneme representation in the first five stages of an R-register;

FIGURE 15 is an illustration of a counter circuit for distinguishingbetween intra-word silence and the end of a word;

FIGURE 16 is an illustration of a circuit for storing an indication ofthe start of a Word;

FIGURE 17 illustrates, in logic equation form, logic circuits forproducing silence and phoneme presence signals;

FIGURE 18 is a diagram and logic equation of a logic circuit forproducing a word end signal;

FIGURE 19 is a partial timing diagram illustrating certain controlsignals of the system;

FIGURE 20 shows a control one-shot circuit together with its input logiccircuit in logic equation form which is triggered at the start of eachspoken word;

FIGURE 21 illustrates an inverter which receives the output signal fromthe one-shot of FIG. 20;

FIGURE 22 illustrates a control flip-flop together with its input logiccircuit in logic equation form which stores an indication that a spokenword is in progress;

FIGURE 23 illustrates another control flip-flop and its input logiccircuit in logic equation form which stores an indication that thespoken Word has ended;

FIGURE 24 illustrates another control flip-flop and its input logiccircuit in logic equation form which enables a serial shift of a storageregister (R-register) for comparing a new phoneme sequence with thestored phoneme sequences;

FIGURE 25 illustrates the first five stages of a register circuit(R-register) together with the input logic circuits shown in logicequation form;

FIGURE 26 illustrates one sector of a memory drum employed in theillustrated embodiment of the invention;

FIGURE 27 illustrates the entire R-register together with the inputlogic circuits illustrated in logic equation form;

FIGURE 28 illustrates portions of a memory unit;

FIGURE 29 illustrates various clock pulse driver circuits with the inputlogic gating circuits thereof shown in logic equation form;

FIGURE 30 illustrates in logic equation form the equivalent gatingcircuits of various parenthetical terms;

FIGURE 31 illustrates a six-stage bit counter with the input logiccircuits thereof shown in logic equation form;

FIGURE 32 illustrates a six-stage sector counter with the input logiccircuits thereof shown in logic equation form;

FIGURE 33 is a diagram of a logic circuit which developes a phonemesampling pulse;

FIGURE 34 illustrates a double-pole, double-throw, Load-Operate switch;

FIGURE 35 illustrates a four-stage track counter with the input logiccircuits thereof shown in logic equation form;

FIGURE 36 illustrates a flip-flop circuit with its input logic circuitshown in logic equation form which forms a scale of two counter forcounting down the drum revolutions;

FIGURE 37 illustrates a flip-flop circuit together with its input logiccircuit shown in logic equation form which indicates that a comparisonhas been found between a received phoneme sequence and a phonemesequence stored in the memory;

FIGURE 33 illustrates a gating circuit which produces a timed comparisonsignal;

FIGURE 39 illustrates a gating circuit which produces an unsuccessfulsearch signal;

FIGURE 40 illustrates an eleven-stage output register together with itsinput logic circuits shown in logic equation form;

FIGURE 41 illustrates a Load control flip-fiop together with its inputlogic circuit partly in logic equation form;

FIGURE 42 illustrates another Load control flip-flop together with itsinput logic circuit shown in logic equation form;

FIGURE 43 illustrates a bank of push-button switches for placing a trackaddress in the track counter of FIG. 35 during a Load operation;

FIGURE 44 illustrates a bank of double-pole, doublethrow switches forsetting up a representation of the address of the sector in which a newWord is to be stored during a Load operation;

FIGURE 45 illustrates a bank of push-button switches for placing a worddesignator corresponding to a new word into the output register; and

FIGURE 46 illustrates a logic circuit for producing a sector addresscomparison signal during a Load operation.

Shown in FIG. 1 is a block diagram of an illustrative embodiment of asignal recognition system of the present invention. A phoneme detector101 furnishes input signals to the present system. Details of thephoneme detector are not shown herein since it is merely one example ofa source of signals which may be recognized by the system. An example ofa phoneme detector is shown in the above-mentioned Patent No. 2,646,465.

The heavy interconnecting lines in FIG. 1 indicate a plurality ofseparate conductors, which will be referred to as cables. Thus input tothe system from the phoneme detector is by way of a cable 102 comprisinga plurality of phoneme lines, each of the lines corresponding to arespective one of the phonemes. The phoneme input signals are mutuallyexclusive. That is, there can be only one phoneme signal present at anygiven time. For purposes of a present explanation it will be assumedthat the cable 102 consists of 32 lines corresponding to 32 respectiveseparate phonemes.

The phoneme lines of cable 102 from the phoneme detector are connectedto respective input terminals of an encoder 103. (A specific structureof encoder 103 is illustrated in logic equation form in FIG. 10.) Theencoder 103 converts each phoneme signal received on any one of the 32phoneme lines to a five-bit binary character which is immediately storedin a register 104 designated the A-register. The A-register is afive-stage register which receives the binary signals in parallel via acable 105 from the encoder. (An embodiment of A- register is shown inFIG. 11.)

To insure that a phoneme has persisted for at least a predetermined timeand to thus distinguish it from noise or other spurious signals, aregister 106 designated the B-register is provided for storing theencoded representation of the previous phoneme. (An embodiment of B-register is shown in FIG. 12.) The contents of the A- register arecompared with the contents of the B-register by means of a circuit 107designated a comparison circuit C4, the output terminals of A and Bregister being connected to the comparison circuit C-l by a pair ofcables 108 and 10). (A specific structure of comparison circuit C-l isillustrated in FIG. 13.) If the information representing states of thestages of the A and B registers are the same, the phoneme signal haspersisted for two sample times and the comparison circuit C-l producesan arming potential on a lead 113 which partially enables a transfercircuit 117. At the same time a comparison is made between the stages ofthe A-register and the first five stages of a phoneme assembly register113, designated the R-register. (The first five stages of R-register areshown in FIG. 25.) A comparison between the Aregister and the first fivestages of the R-register is made to insure that the phoneme is notstored twice in succession even though it has persisted for two or moresample times. This comparison is made by a circuit 114 designated acomparison circuit C-2 which is connected to the stages of theA-register by the cable 108 and to the first five stages of theR-register by a cable 115. (An embodiment of comparison circuit C-2 isshown in FIG. 14.) If the information representing states of the stagesof the A- register and the first five stages of the R-register are thesame then no new phoneme is present and the phoneme of the presentsample time is ignored. If however they are different a new phoneme ispresent and the comparison circuit C-2 produces an arming potential on alead 116 connected to an input terminal of the transfer circuit 117.This arming potential completes the enablement of the transfer circuit117. (The transfer circuit 117 comprises the logic input circuit to thefirst five stages of R-register as illustrated in logic equation form inFIG. 25.) Thus when the two conditions are met, namely, that the encodedphoneme in A-register is the same as that in the B-register butdifferent from the encoded phoneme in the first five stages of theR-register, the new phoneme is to be accepted and the transfer circuit117 is enabled to cause the transfer of the new encoded phoneme in theA-register to the first five stages of the R-register in response to asample signal which occurs each sample time (approximately every 20milliseconds). (Simultaneously the new encoded phoneme in A-register istransferred, via a transfer circuit 111 and a cable 112, to theB-register where it is then available for comparison with the nextphoneme.) (The transfer circuit 111 comprises the logic input circuit tothe stages of B- register as illustrated in logic equation form in FIG.12.)

In the illustrated embodiment of the invention the R- register comprises35 stages, that is, seven columns of five stages each. (An embodiment ofR-register is illustrated in FIG. 27.) Thus the R-register is capable ofassembling and storing a sequence of seven phonemes. Simultaneous withthe transfer of a new phoneme representation from the A-register to thefirst column of stages of the R-register the R-register undergoes acolumn-by-column shift to the right, in other words, the phonemerepresentation contained in the first column of stages of the R-registeris transferred to the stages of the second column of the R-register, andso forth. This assembly of a sequence of phoneme representations in theR-register continues until the spoken word has ended or until theR-register is filled. If it should be desirable to recognize wordscomprising a sequence of more than seven phonemes the R-register may beexpanded to a correspondingly greater number of columns of stages.

Once a sequence of phoneme representations have been assembled in theR-register it can then be identified. This identification isaccomplished by providing a memory unit 119 in which is stored adictionary of phoneme sequences of all the allowable ways of saying eachword of the vocabulary of words to be recognized. Associated with thephoneme sequences stored in the memory unit is a unique binaryrepresentation for the spoken word called the word designator, the sameword designator being associated with each of the phoneme sequenceswhich are alternative ways of saying the same word.

In the illustrated embodiment of the invention the memory unit 119'includes a magnetic drum (shown in FIG. 28). Thus the information storedthereon is available serially as the drum rotates. A Read-Write circuit123 provides access to the memory. (The Read-Write circuit 123 comprisesWrite Input, Head Switching and Driving, and Read Output circuits asshown in FIG. 28.)

Thus when assembly of the unknown phoneme sequence in the R-register hasbeen completed, logic connections are made which cause an end-aroundserial shift of the information in the R-register. (R-1 to R-2, R-Z toR-Ts, and 11-35 to R-l.) As the serial shift proceeds the binaryrepresenting state of stage R-35 is compared with the respective bits ofthe stored encoded phonemes as they are read from the drum. A trackcounter and a head switching circuit are provided to automaticallyswitch tracks so that the entire memory may be searched.

A circuit 121) designated a comparison circuit C-3 compares the phonemesignals read from the memory with the state of stage R-35 of R-register.(An embodiment of comparison circuit 0-2 is illustrated in FIG. 37.)When a comparison is found a signal from the comparison circuit C-3 armsa transfer circuit 121 and the word designator which is associated withthe stored phoneme sequence is read out of the memory and into an outputregister 122 (Or-register) where it is available for use by externalequipment. (An embodiment of the Orregister is shown in FIG. 40. Thetransfer circuit 121 comprises the logic input circuit of Or-register.)

The system of the present invention is also adapted to perform the taskof loading phoneme sequences into the memory unit. This is a usefulfeature for it allows an operator to readily store in the memory thephoneme sequences corresponding to his way of speaking the words of thevocabulary. To accomplish this, the operator speaks the new word intothe microphone of the phoneme detector and the system detects thephonemes of the word and stores them in the R-register in the manneroutlined hereinbefore. The operator also places the corresponding worddesignator in the output register 122. He also sets addressing circuitsof the memory unit so that the new phoneme sequence will be recorded ina chosen location in the memory. The phoneme sequence is then writteninto the memory from the R-register followed by the word designator fromthe output register 122.

The various timing and control elements necessary for the system of thepresent invention are represented in FIG. 1 by a block 124 designatedTiming and Control. (Specific embodiments of the various timing andcontrol circuits are illustrated in FIGS. 15-18, 20-24, 38, 39 and41-46.) Timing and control signals which emanate from circuit 124 areapplied to various elements of the system as shown in the specificillustrations of the elements.

A general description of the signal recognition system of the presentinvention has been given above in connection with FIG. 1. The individualelements comprising the system will be described more specifically afterthe following brief description of basic circuit elements.

The following circuits find employment in the system: AND gate, OR gate,flip-flop, clock-pulse driver, phase inverter, and one-shot. A signal inthe system which is at an arming or enabling level will be spoken ofhereinafter as being up; when a signal is at a disarming level it willbe spoken of as being down.

Shown in FIG. 2 is the symbol representative of an AND gate. An AND gateis a well-known logic element which produces an arming signal at itsoutput terminal only when the signals applied to its plurality of inputterminals are simultaneously at an arming level. Thus an output signal Hof an AND gate 201 is up if each of a pair of signals F and I applied toits input terminals is up, but is down if either of the signals F or Jis down. For convenience and clarity and to simplify the drawingsextensive use of the logic equations will be made as illustrative of thelogic circuitry. The usual convention of the indicated product for theAND function will be employed. Thus the equation H =F] in FIG. 2 isillustrative of the AND gate 201 equally as well as the symbol shown. (Asuitable embodiment of an AND gate is shown in FIG. 5 in a US. patentapplication 8,391, filed February 12, 1960, by R. R. Johnson for a DataProcessing System, and assigned to the same assignee as the presentinvention.) Certain AND gates used in the circuits of the presentinvention are required to produce an output pulse in response to a gatedinput pulse. Such gates are used in logic circuits which are connectedto the input terminals of the register flip-flops as will be explainedmore fully hereinafter. (A suitable embodiment of a pulse AND gate isshown in FIG. 10 of the above-mentioned patent application Serial No.8,391 wherein it is designated 21 Register Transfer circuit.)

A symbol of an OR gate 301 and the corresponding logic equation is shownin FIG. 3. An OR gate is a wellknown circuit which produces an outputsignal in response to an input signal at any one or more of its severalinput terminals. The usual convention of a plus sign for the inclusiveOR function will be used. Thus the equation h=f+j, which represents thegate 301, indicates that the signal It will be up if either of thesignals 7 or i is up or if both are up. (A suitable embodiment of an ORgate is shown in FIG. 6 of the above-mentioned US. patent ap plicationSerial No. 8,391.)

Shown in FIG. 4 is an example of a flip-flop circuit. The flip-flop is awell-known circuit which provides temporary storage of a binary bit orprovides storage of a control signal. The flip-flop comprises a bistabledevice 401, a pair of OR gates 402 and 493, and a pair of AND gates 404and 465. The bistable device 401 is capable of either of two stablestates of operation. Thus it may assume a 1 representing or set state ora representing or reset state. The bistable device 401 assumes its setstate in response to a pulse applied to a set input terminal 406. In itsset state the bistable circuit 401 produces a signal 77 at a set outputterminal 407 which is up or at an arming level and a signal fi at areset output terminal 408 which is down or at a disarming level.

The bistable circuit 491 assumes its reset state when a signal isapplied to a reset input terminal 4-99. When the bistable circuit 491 isin its reset state the signal T is up and the signal 17 is down. It isto be noted that the output signals ff and 57 are complementary, thatis, when one is up the other is down.

Signal terms which are preceded by an or a it are input signals,ordinarily, from logic circuits. The flip-flop circuit of FIG. 4 isadapted to receive five different input signals: a i set input signal,an set input signal, a clock pulse signal C, an reset input signal, anda reset input signal. If the set input signal is up on the occurrence ofthe clock pulse C the gate 404 produces a pulse which is passed by thegate 402 and applied to the set input terminal 406 of the bistablecircuit 401 thus triggering the circuit to its set state. Similarly ifthe reset input signal is up on the occurrence of the clock pulse C theAND gate 405 produces a pulse which is applied to an input terminal ofthe OR gate 403 which in turn produces a reset signal at the resetterminal 499 which causes the bistable circuit 401 to assume its resetstate. The input signals are ordinarily pulses which have been producedby externally clocked logic circuitry.

A symbolic representation of the flip-flop circuit of FIG. 4 is shown inFIG. 5 and this symbol will be employed to represent the registerflip-flops and the control flip-flops hereinafter. (An embodiment of aflip-flop circuit is shown in FIG. 4 of the aforementioned US. patentapplication Serial No. 8,391.)

A symbolic representation of a clock pulse driver circuit is shown inFIG. 6 as a clock pulse driver 661. The clock pulse driver producesclock pulse signals to drive other clock pulse drivers or forapplication to the clock pulse input terminal of flip-flops and to pulselogic circuits for controlling the entry of data into flip-flops and thetransfer of data between the flip-flops of registers. The clock pulsedriver responds to an input clock pulse C to produce or generatecorresponding output clock pulses. The operation of a clock pulse driveris controlled by an input signal, ordinarily the output signal of alogic circuit. When this signal is up on the occurrence of an inputclock pulse C an output clock pulse is produced. When this signal isdown the circuit is inhibited. (A suitable embodiment of the clock pulsedriver is shown in FIG. 3 of the above-mentioned US. patent applicationSerial No. 8,391.)

Shown in FIG. 7 is a symbolic representation of an inverter circuit 701.Such a circuit is used to produce complementary arming and disarminglevels of an input signal. Thus if a signal Z is applied to the inputterminal of the inverter circuit a pair of output signals Iz and T5 areproduced, the signal Iz being the inverted version of the signal Z. Inother words, if the signal Z is up the signal 12 is down and the signalIE is up. If the input signal Z is down the signal Iz is up and thesignal IE is down. (A suitable embodiment of an inverter circuit shownin FIG. 7 of the above-mentioned patent application Serial No. 8,391.)

Another basic circuit used in the present invention is the well-knownone-shot circuit. The symbolic representation of a one-shot 801 is shownin FIG. 8. The oneshot is a circuit having stable and astable states ofoperation. A positive input pulse triggers the one-shot circuit to itsastable state in which it remains for a predetermined designed timeafter which it returns to its stable state. The one-shot circuit isuseful in timing various operations of computer circuits. In theone-shot circuit shown in FIG. 8 when an input signal Os is up or at anarming level upon the occurrence of a clock pulse C, the one-shot istriggered to its astable state in which state an output signal 6? isdown or at a disarming level. (A suitable embodiment of a one-shotcircuit is shown in FIG. 11 of the above-mentioned patent applicationSerial No. 8,391.)

Since the logic circuits of the system of the invention are to a greatextent shown in symbolic and logic equation form it is appropriate atthis point to clearly define the terminology used. It is also pointedout that while logic equations are employed herein to define the logicstructures of the system it is known in the art that such logicequations define the structure to the same extent as block diagrams ofsuch logic structure. For example a logic equation =DT=D13 Ss+Sp Ss (seeFIG. 36) illustrates a logic circuit which comprises a first AND gatewhich receives the signals D13 and Ss, a second AND gate which receivesthe signals Sp and gs and an OR gate which receives the output signalsfrom the first and second AND gates and produces the signal *m (thereset input signal to a flip flop circuit). For convenience a mnemonicterminology has been adopted consisting of one or more letters. Only thefirst letter of a signal designation is capitalized. For example termCab is the output signal of a comparison circuit for comparing thecontents of A and B registers.

Before proceeding to a description of the details of the elements of thesystem the signals which are used and developed in the system will bedefined. For convenience and ready reference the signal definitions arelisted below in the alphabetical order of the signal designations. Thenumber of the figure in which the circuit of origin of the signal isshown is also given.

Signal Definitions A1 A5, E K5: These are the respective set and resetoutput signals from the flip-flops or stages of the A-register (FIG.11). The A-register contains the binary coded representation of thecurrent phoneme received from the encoder.

B1 B5, FT E5: These are the respective set and reset output signals fromthe stages of the B-register (FIG. 12). The B-register contains thebinary coded representation of the previous phoneme which was in theA-register at the last sample time.

Cab: This is a comparison signal from the comparison circuit C-l (FIG.13). This signal is up when the encoded phonemes in A and B registersare the same.

m: This is a comparison output signal from the comparison circuit C-2(FIG. 14). This signal is up when the encoded phonemes in the A-registerand the first five stages of the R-register are different.

Cdo: This is an output signal from a clock pulse driver circuit Cd (FIG.29). This signal causes a serial shift in the Or-register. This serialshift enables the output register to receive the word designator fromthe memory during normal signal recognition operation and provides aword designator for recording in the memory during a Load operation.

Cdp: This is the output signal from a clock pulse driver circuit Cd2(FIG. 29). This signal causes a bit-parallel, character-serial shift ofthe R-register when the encoded phonemes are being assembled therein.

Cds: This is an output signal from a clock pulse driver circuit Cd-3(FIG. 29). This signal causes a completely serial shift of theR-register when the phoneme sequence assembled therein is compared withthe stored phoneme sequences in the memory and during a Load operationfor recording the phoneme sequence in the memory.

Cdt: This is an output signal from a clock pulse driver circuit Cd-4(FIG. 29). This signal causes a track counter (D-l3 D16) to count oncefor every revolution of the drum.

Cdl: This is an output signal from a clock pulse driver circuit Cd1(FIG. 29). This signal causes a sector counter (D7 D-12) to count onceevery drum word or sector time.

Cmr: This is a signal from a logic gating circuit which may be used toindicate to external equipment that comparison was found between thecontents of the R-register and phoneme part of the drum word or sectorlast read from the memory (FIG. 38).

Cp: This signal is the bit clock pulse which originates from a clocktrack on the drum of the memory unit. It occurs at intervals ofsubstantially four microseconds (FIG. 28).

Csd: This is the output signal from a sector address comparison circuit(FIG. 46). This signal indicates a comparison between a set of switchesS-l 8-6 and the sector counter (D-7 D12). When this comparison is foundthe next sector to pass under the writing head is the one in which thecontents of R-register and the Or-register are to be written during aLoad operation.

Ct: This is an output signal from a logic circuit which receives signalsfrom an address counter (FIG. 30). Each track on the drum memorycontains 40 sectors each having fifty bit positions designated t1 r50.The signal Ct is up during r46 time of sector 40. Among other things thesignal Ct arms a circuit for counting the track counter (D-13 D-16).

D1 D6, D 1 DE: These are the set and reset output signals respectivelyof the stages D-l D-6 of a D-counter of the memory unit which form asix-stage hit counter (FIG. 31). These signals are applied to logicgating circuits for producing enabling or arming signals atpredetermined bit times.

D7 D12, 57 D12: These signals are the respective set and reset outputsignals from the stages D7 D-12 of the D-counter which form a six-stagesector counter (FIG. 32). In the illustrated embodiment of the inventionthere are 40 sectors in each track.

D13 D16, 5T3 fill: These are the respective set and reset output signalsfrom the stages D-13 D-i6 of the D-counter which form a four stage trackcounter (FIG. 35). Logic levels. derived from these signals switch thereading and writing circuits among the drum tracks. In the illustrativeembodiment of the invention there are 13 tracks.

D17, W: These are respective set and reset output signals of the D-17stage of the D-counter which forms a one stage drum revolution counter(FIG. 36). The mag- I0 netic drum of the illustrated memory makes onerevolu tion substantially every 10 milliseconds. The stage D-17 is usedto count down the drum revolutionsby a factor of 2 for generating asample signalTl every 20 milliseconds.

Iywp: This is the output signal of an inverter circuit (FIG. 21). Thissignal is used to clear the B-register and the R-register at the startof each spoken word. It is also used to control the generation of theclock pulse Crip.

Kml: This is a signal from a push-button which initiates the loading ofa new phoneme sequence word into the memory by setting a flip-flop L-l(FIG. 41).

Ksd13 Ksdlo, Krdl3 Krd16: These are the the output signals from a set ofswitches of a track selection circuit (FIG. 43). These signals selectthe track in which a new word is recorded during loading of the memory.

Ksorl Ksorll, Krorl Krorll: These are output signals from a set ofswitches of a word designator selection circuit (FIG. 45). These signalsrepresent the word designator which is recorded in the memory togetherwith a new word.

L, L: These are signals from a Load-Operate switch which conditions thecircuits of the system for normal signal recognition operation (L up) orfor loading new phoneme words into the memory (L up) (FIG. 34).

L1, fi: These are respective set and reset output signals from a Loadoperation initiating flip-flop L1 which stores the load signal Km untilthe timing of the system is correct for the Load operation to begin(FIG. 41).

L2, L5: These are respective set and reset output signals from a loadcontrol flip-flop L-2 (FIG. 42). These signals enable the system forwriting the encoded phoneme sequence of a new word into the memory.

M, M: These are respective set and reset output signals of a read outputcircuit flip-flop M-l which receives signals read from the drum (FIG.28).

Mar, rm: These are respective set and reset output signals from aflip-flop Mer-l for indicating when a comparison is found between thecontents of R-register and a phoneme sequence read from the drum (FIG.37). During the memory search the flip-flop M6l1 is triggered to its setstate every time. During the scanning of the next sector the stage Mer-lis triggered so that Mer goes down upon the occurrence of the first pairof phoneme bits which fail to compare. If the signal Mer is still up atsome r46 time this means that the phoneme sequence of the correspondingsector is the same as the phoneme sequence to be recognized which isbeing circulated in the R-register.

Op, 6 5: These are the output signals of an origin pulseinverter-amplifier which receives signals from a read head adjacent anorigin track of the magnetic drum (FIG. 28). The Op pulse is up for oneclock time (r50) each drum revolution and it is used to synchronize thebit and sector counters (D-l D-12 of the D-counter).

Orl Orll, 61 i Orll: These are respective set and reset output signalsfrom the Or-register stages Or1 Or-ll (FIG. 40). The Or-register acceptsthe word designator which is read from the memory immediately followinga successful comparison between a phoneme sequence stored in the memoryand the phoneme sequence being circulated in the R-register. In the Loadmode of operation the Or-register receives the word designatorcorresponding to the new word for recording in the memory.

P1 P3, Fl: P 3: These are respective set and reset output signals from athree stage binary presence counter designated a P-counter (FIG. 15).The P-counter is part of a circuit for detecting the start of a spokenword and for distinguishing between significant silence during a wordand silence indicating the end of a Word.

Ph: This is the output signal of a logic circuit which receives signalsfrom the stages of A-register (FIG. 17).

11. IN A SYSTEM FOR IDENTIFYING A PLURALITY OF SEPARATE ITEMS OFINFORMATION; EACH ITEM COMPRISING A UNIQUE SEQUENCE OF PREDETERMINEDELEMENTS OF INFORMATION, EACH RECEIVED ELEMENT PERSISTING A VARIABLELENGTH OF TIME, MEANS FOR CONVERTING A RECEIVED SEQUENCE OF VARIABLELENGTH INFORMATION ELEMENTS TO A CORRESPONDING SEQUENCE OF EQUALLYSPACED INFORMATION ELEMENTS COMPRISING: SAMPLING MEANS FOR EXAMININGEACH RECEIVED SEQUENCE OF ELEMENTS AT EQUALLY SPACED SAMPLE TIMES ANDFOR PRODUCING AN ELEMENT REPRESENTATION OF EACH ELEMENT ONLY IF ITPERSISTS FOR A PREDETERMINED NUMBER OF SAMPLE TIMES AND ONLY IF IT ISDIFFERENT FROM THE ELEMENT CORRESPONDING TO THE LAST PRODUCED ELEMENTREPRESENTATION; AND MEANS FOR RECEIVING AND ASSEMBLING THE ELEMENTREPRESENTATIONS PRODUCED BY SAID SAMPLING MEANS.